Method and arrangement for compensation of a magnetic bias field in a storage layer of a magnetoresistive memory cell

ABSTRACT

An arrangement is described for compensation of a magnetic bias field in a storage layer of at least one magnetoresistive memory cell provided in a semiconductor device. In this arrangement, at least one compensation layer that is provided with a magnetization compensates for the bias field in the storage layer. A method is also described for compensation of a magnetic bias field in a storage layer of a magnetoresistive memory cell provided in a semiconductor device. A step is provided for applying a ferromagnetic compensation layer. In another step, a bias field is measured in terms of magnitude and direction. In another step, the bias field is compensated by magnetization of the compensation layer.

BACKGROUND

1. Field

Embodiments of the present invention relate to arrangements forcompensation of a magnetic bias field in a storage layer of amagnetoresistive memory cell provided in a semiconductor device. Inaddition, the invention relates to methods for compensation of such abias field.

2. Background

A memory cell based on the magnetoresistance effect conventionally hasbeen realized by a stack of two thin ferromagnetic layers, with anintervening nonferromagnetic isolating layer having a thickness of aplurality of atomic layers. One of the two ferromagnetic layers iscomposed of a hard-magnetic material, typically a cobalt-iron alloy.With a magnetization which is constant in terms of magnitude anddirection, it functions as a reference layer. The second ferromagneticlayer made of a soft-magnetic material, typically a nickel-iron alloy,forming a storage layer. Its magnetization is oriented unidirectionally,or in oppositely directed fashion with respect to the magnetization ofthe reference layer, corresponding to data content of the memory cell.

When a unit of data is written to the memory cell, the direction of awrite current in an address line of the memory cell determines theorientation of the magnetization in the storage layer with respect tothe magnetization of the reference layer. The material of the isolatinglayer is a dielectric in the case of a memory cell configuration basedon a tunneling effect (MTJ, magnetic tunnel junction). In this case, theeffect underlying the read-out of the memory cell is that the frequencyof electrons crossing through the isolating layer (tunnel barrier) ishigher in the case of identical orientation of the magnetization of thetwo ferromagnetic layers than in the case of opposite orientation.

The effect underlying the read-out of the memory cell is thus based oninternal properties of the magnetized ferromagnetic layers, but not on adirect interaction of the magnetic fields generated by the two layers.Their interaction, or ferro- and antiferromagnetic coupling, influencesthe operating behavior of the memory cell. In this case, the term“ferromagnetic coupling” denotes that proportion of the interaction thatpromotes an orientation of the magnetization of the storage layerparallel to the orientation of the magnetization of the reference layerand inhibits a changeover of the magnetization of the storage layer in adirection opposite to the magnetization of the reference layer. The term“antiferromagnetic coupling” denotes that proportion of the interactionthat inhibits a storage layer orientation parallel to the orientation ofthe magnetization of the reference layer and promotes a changeover ofthe magnetization direction of the storage layer in a direction oppositeto the magnetization direction of the reference layer.

The ferro- and antiferromagnetic couplings between the reference layerand storage layer of one and the same memory cell, but also of adjacentmemory cells, make contributions to a magnetic bias field within andoutside a semiconductor device having magnetoresistive memory cells. Ina storage layer permeated by such a bias field, the bias field effects ashift in the field strengths required for changing over themagnetization direction, the so-called coercive field strengths. Thisshift requires an asymmetry in the magnetic fields required for writingand thus also in the write currents.

This effect is illustrated by the two illustrations in FIG. 2, which isreduced to a one-dimensional changeover of the storage layer forsimplification. In this case, H_(C1) and H_(C2) designate magnitudes ofcoercive field strengths required for changing over the magnetizationbetween the states M₀ and M₁ in the absence of a bias field, and H_(B)denotes the magnitude of the magnetic bias field.

The upper part of FIG. 2 illustrates the magnetization reversal curve ofa storage layer for the case of an absent bias field. The specificcoercive field strengths H_(C1) and −H_(C1) are symmetrical with respectto the magnetization axis. The lower part of FIG. 2 illustrates amagnetization curve relative to a magnetic field H(I) generated by thewrite current I in the case of superposition with a bias field actingoppositely to the magnetic field axis. For such a magnetic field, themagnetization curve appears to be shifted by the magnitude H_(B) counterto the direction of H_(B).

If the bias field and the magnetization of the storage layer areunidirectional, then a changeover of the magnetization requires amagnetic field whose magnitude results from the sum of the specificcoercive field strength of the storage layer and the magnetic fieldstrength of the bias field. In this case, the bias field, given apredetermined maximum write current, reduces reserves with regard to areliable changeover of the magnetization in the storage layer of thememory cell.

If the bias field is directed oppositely to the magnetization of thestorage layer, then a magnetic field having a magnitude corresponding tothe magnitude of the specific coercive field strength of the storagelayer reduced by the magnitude of the magnetic field strength of thebias field already suffices for changing over the magnetization.

In this case, even smaller magnetic fields may compel a changeover ofthe magnetization. A reserve with respect to an undesired changeover ofthe magnetization is thus reduced. Such magnetic fields may be caused onthe one hand by extreme interference fields with a source outside thesemiconductor device. A second source of such magnetic fields is, forinstance, magnetic fields generated by write currents of adjacent memorycells within the semiconductor device.

The ferromagnetic coupling which underlies the bias field in the storagelayer is determined by the distance between the two ferromagneticlayers, the thickness of the storage layer, and also the roughness ofthe layers forming the memory cell.

In this respect, reference is made to L. Néel, Comptes Rendus Acad. Sci.255, 1676 (1962) and, in particular, formula (1) in A. Anguelouch etal., Two-dimensional magnetic switching of micron-size films in magnetictunnel junctions, Applied Physics Letters, Vol. 76, No. 5, 2000.

In this case, the orientation of the bias field is not necessarilyeffected in a direction parallel to the orientation of the magneticfields generated by the write currents, but rather may also have acomponent which is orthogonal thereto and parallel to the storage layer.In this respect, reference is made in particular to FIG. 2 a in A.Anguelouch et al., Two-dimensional magnetic switching of micron-sizefilms in magnetic tunnel junctions, Applied Physics Letters, Vol. 76,No. 5, 2000. The physical causes of this effect are not completelyknown, but the bias field does not change in terms of magnitude anddirection during a lifetime of the memory cell.

In particular, the roughness of the layers yields variable and at thesame time difficult-to-predict proportions with respect to the biasfield. In this case, the roughness contribution varies betweensemiconductor devices, even of identical designs, which are producedfrom different wafers, while it is similar in the case of semiconductordevices which are produced from the same wafer.

FIG. 3 illustrates a diagrammatic cross section through amagnetoresistive memory cell. An isolating layer 2 lies between areference layer 3 and a storage layer 1. Dividing the reference layer 3into a lower and an upper reference sublayer 3 a, 3 c with a nonmagneticintermediate layer 3 b produces a magnetic leakage field, which mayproduce an antiferromagnetic coupling indicated by the arrow 5. Thecauses of the ferromagnetic coupling, that is to say the roughness ofthe layers, and also the thickness of isolating layer and storage layer,are indicated by the arrow 4.

In order to reduce the bias field, at the present time attempts arebeing made, on the one hand, to reduce the ferromagnetic coupling. Onthe other hand, attempts are being made to set the antiferromagneticcoupling toward a compensation of the bias field.

A reduction of the ferromagnetic coupling by using a thicker storagelayer is confronted with the obstacle of the larger switching currentswhich are then necessary for changing over the magnetization. Equally,the distance between the ferromagnetic layers is prescribed by therequirements made of the electrical resistance of the memory cell and bythermodynamic requirements.

Limits are imposed on compensation by means of the antiferromagneticcoupling since the latter exhibits a stable behavior only given low netmoment. For a maximum effect, one of the reference sublayers would haveto be dispensed with, as a result of which the stability of thereference layer would also be impaired. Furthermore, it cannot be usedto effect compensation of a ferromagnetic coupling which is broughtabout for instance as a result of magnetorestriction during a patterningoperation of the memory cell or the semiconductor device and is rotatedwith respect to the magnetization direction of the storage layer.Furthermore, the antiferromagnetic coupling is unsuitable, in the caseof semiconductor devices produced from different wafers, forcompensating for contributions of the ferromagnetic coupling—broughtabout by the roughness of the layers—which regularly deviate from oneanother.

SUMMARY

An arrangement is disclosed that enables a compensation of a bias fieldin the storage layer of a magnetoresistive memory cell provided in asemiconductor device and in which the geometry of the memory cellremains unchanged. Methods also are obtained that enable saidcompensation to be obtained.

An arrangement is disclosed for compensation of a magnetic bias field ina storage layer of at least one magnetoresistive memory cell provided ina semiconductor device. In this arrangement, at least one compensationlayer is provided with a magnetization that compensates for the biasfield in the storage layer.

A method is described for compensation of a magnetic bias field in astorage layer of a magnetoresistive memory cell provided in asemiconductor device. A step is provided for applying a ferromagneticcompensation layer. In another step, a bias field is measured in termsof magnitude and direction. In another step, the bias field iscompensated by magnetization of the compensation layer.

Another method also is described for compensation of a magnetic biasfield in a storage layer of a magnetoresistive memory cell provided in asemiconductor device. A bias field is measured in terms of magnitude anddirection. The bias field is compensated by application of acompensation layer, which has a magnetization that compensates for thebias field in the storage layer.

The invention is explained in more detail below with reference to thedrawings, the same reference symbols being used for mutuallycorresponding components.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a diagrammatic illustration of an exemplary arrangementaccording to a first and a second exemplary embodiment of the invention,

FIG. 2 is a simplified illustration of the magnetization reversal curveof a storage layer respectively in the absence of a bias field and withan effective bias field, and

FIG. 3 is a diagrammatic illustration of a magnetoresistive memory cell.

FIGS. 2 and 3 have already been explained in the introduction.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

The following reference symbols are used consistently in the descriptionof the figures as described in the background and as set forth herein:

-   -   M Magnetization    -   H(I) Magnetic field strength of a magnetic field generated by a        write current I    -   H_(C1) Magnitude of a specific coercive field strength    -   M₀ First magnetization    -   M₁ Second magnetization    -   H_(B) Magnitude of the magnetic field strength of the bias field    -   1 Storage layer    -   2 Isolating layer    -   3 Reference layer    -   3 a Upper reference sublayer    -   3 b Intermediate layer    -   3 c Lower reference sublayer    -   4 Representation of the ferromagnetic coupling    -   5 Representation of the antiferromagnetic coupling    -   6 Memory cell    -   7 Semiconductor device    -   8 Housing    -   9 Compensation layer within the semiconductor device    -   10 Compensation layer outside the semiconductor device    -   11 Passivation layer

FIG. 1 illustrates a simplified cross-section through a semiconductordevice 7 having magnetoresistive memory cells 6, with the cross-sectionnot being true to scale and being restricted to the illustration ofcertain features that are considered as being generally more significantwith regard to the invention.

The memory cells 6 are in each case constructed from storage, isolatingand reference layers 1, 2, 3 and, in the example illustrated, arearranged in a single layer of the semiconductor device 7. A passivationlayer 11 is applied parallel to a memory cell layer formed from thememory cells 6.

Ferromagnetic coupling between the reference and storage layers 3, 1 ofthe memory cells 6 gives rise to a magnetic bias field.

The components illustrated by broken lines are omitted for a firstexemplary embodiment with a compensation layer 9 provided within thesemiconductor device 7. In the first exemplary embodiment, thecompensation layer 9 is applied parallel to the storage layers 1 in amanner isolated from the memory cells 6 by a passivation layer 11 andmay be magnetized in such a way that the magnetic field of themagnetization compensates for the magnetic bias field in the storagelayers 1. In order to obtain a magnetic field that is generated by themagnetization of the compensation layer 9 and is as far as possibleidentical in terms of magnitude and direction in all the storage layers1 of the semiconductor device 7, the compensation layer 9 preferablycovers an entire cross-sectional area of the semiconductor device 7.

A second exemplary embodiment also comprises components illustrated bybroken lines and has a compensation layer 10 provided outside thesemiconductor device 7 and a housing 8, which at least partiallysurrounds the semiconductor device 7, the compensation layer 9 providedwithin the semiconductor device 7 being obviated.

For the reasons mentioned above, the compensation layer 10 appliedoutside the semiconductor device is also preferably applied parallel tothe storage layers 1 and preferably covers at least an entire surfaceparallel to the storage layers 1.

Thus, in the case of an arrangement of the type according to embodimentsof the invention, a bias field which takes effect in a storage layer ofa magnetoresistive memory cell situated in a semiconductor device iscompensated for by means of a magnetostatic leakage field (compensationfield hereinafter) of at least one suitably magnetized compensationlayer.

The compensation layer may be applied outside and/or within thesemiconductor device.

If a compensation layer is applied within a semiconductor device, thenthis is preferably done at the wafer level by means of the technologiesthat are customary for the processing of a wafer and with the materialswhich are used in the fabrication of the memory cells. The magneticproperties of such a compensation layer can be influenced by means of apatterning of the compensation layer.

Within the semiconductor device, the compensation layer, for instanceisolated by means of an SiO₂ layer, may be applied below a memory celllayer having the memory cells.

In the case of semiconductor devices having a plurality of memory celllayers, each memory cell layer may in each case be assigned at least onecompensation layer which is magnetized toward the specific requirementsof the respective memory cell layer. In this case, memory cell andcompensation layers alternate in the layer construction of thesemiconductor device. In a preferred manner, the compensation layer isapplied within the semiconductor device on a first passivation followingthe memory cell layer.

If the compensation layer is applied during or after a process ofhousing the semiconductor device, then in this context it is deemed tobe a compensation layer outside the semiconductor device.

Such a solution is the use of housings made of a ferromagnetic materialor the positioning of the semiconductor device on a suitable carrier.

A preferred embodiment of the arrangement for a compensation layerapplied outside the semiconductor device is a magnetizable lamina or afilm of this type, preferably applied on at least one surface of thesemiconductor device which is parallel to the storage layer. What is ofcrucial importance in this case is that at least one component of themagnetic field runs parallel to the storage layer.

In any event, it is also possible to use an arrangement provided forshielding the semiconductor device against external fields ascompensation layer, or else the compensation layer as shielding of thesemiconductor device.

In order to generate a compensation field which is homogeneous over allthe memory cells, the compensation layer is preferably applied over anentire cross-sectional area of the semiconductor device which isparallel to the storage layers.

A subsequent patterning of the compensation layer enables the fineadjustment of the compensation field. Before the compensation field isadjusted, however, it is necessary to determine it.

The bias field is preferably measured in a test mode of thesemiconductor device by means of a measuring apparatus. In this case,the measuring apparatus controls two magnetic measurement fields ofvariable strength which are parallel to the storage layer and orthogonalwith respect to one another. Depending on said measurement fields, amagnetic-field-dependent, typical characteristic value (measurementvariable hereinafter) of the memory cell, for instance an electricalresistance of the memory cell, is determined and transmitted to anexternal test device. In this case, the measurement fields are generatedin a suitable manner by currents in interconnects of the semiconductordevice which are specially fashioned for this purpose, or with the aidof the existing connecting lines of the memory cell.

The relevant interconnects may be routed toward the outside viaconnections in the same way as a measuring section for measuring themeasurement variable at the semiconductor device. In this case, themeasurement fields are controlled and/or the measurement variable isdetermined by means of a measuring apparatus outside the semiconductordevice.

In a preferred manner, the measuring apparatus is at least partiallyintegrated into the semiconductor device and has in each case at leastone controllable current source, two triangular-waveform generators anda measuring device suitable for the measurement variable. A measurementoperation is only initiated externally and then the measured values forthe measurement variable are transmitted toward the outside.

In this case, the measured memory cell may be one of the functionalmemory cells of the semiconductor device, a reference memory cell or amemory cell provided specifically for this method. Data obtained areused to calculate the compensation field in terms of magnitude anddirection.

According to a first method, the compensation of the bias field iseffected by a compensation layer which has already been applied in or onthe semiconductor device subsequently being magnetized in a mannerdependent on measured values measured for the bias field.

The compensation layer is magnetized in an external magnetic field whosestrength is set in a manner dependent on the initial magnetization curve(initial curve) of the material of the compensation layer in thespecified direction and the values determined for the bias field.

The compensation layer is at least partially composed of a hard-magneticmaterial, which may have a premagnetization. A magnetic field assignedto the premagnetization is superposed on the bias field to becompensated for. Moreover, the magnetization behavior of thecompensation layer does not follow the initial curve of the material.

Thus, in the case of a compensation layer which has already beenpremagnetized, an incorrect value is determined, under certaincircumstances, for the field strength of the external magnetic fieldwhich magnetizes the compensation layer. The bias field is thencompensated for incompletely.

Therefore, in a preferred manner, the bias field is measured again aftera first controlled magnetization of the compensation layer. The measuredvalues obtained can be used to deduce the direction and magnitude of thepremagnetization of the compensation layer. A new value is thereupondetermined for the strength and direction of the external magnetic fieldwhich controls the magnetization of the compensation layer, and thecompensation layer is magnetized again using such a magnetic field.

In the case of this first method according, the compensation layer maybe provided within the semiconductor device or outside the semiconductordevice. It may be patterned, as required, for the purpose of fineadjustment. According to a second method, firstly the bias field ismeasured before a compensation layer which has already beenappropriately magnetized is applied.

The bias field is thus measured with the compensation layer absent andin a manner uncorrupted by such a compensation layer, therebysimplifying the method for compensation of the bias field. Thecompensation is then also preferably effected in a stage of a processfor producing the semiconductor device which is no longer followed by asignificant heating step which alters the magnetic conditions of thesemiconductor device.

On the basis of the transmitted measured values, a prepared compensationlayer which is appropriate in terms of magnitude and direction of thebias field, preferably a prepared film with hard-magnetic sections, isapplied on the semiconductor device.

In this case, in a first variant, the prepared films are present in theform of a first collection sorted in terms of magnitude and direction ofthe magnetization and are applied with uniform orientation.

In a second variant, the prepared films are present as a secondcollection sorted only in terms of the magnitude of the magnetizationand are applied to the semiconductor device with an orientationprescribed by the direction of the bias field.

In a particularly preferred manner, the prepared compensation layer,that is to say also the prepared film, has an inscription whichidentifies the semiconductor device.

The foregoing disclosure of the preferred embodiments of the presentinvention has been presented for purposes of illustration anddescription. It is not intended to be exhaustive or to limit theinvention to the precise forms disclosed. Many variations andmodifications of the embodiments described herein will be apparent toone of ordinary skill in the art in light of the above disclosure. Thescope of the invention is to be defined only by the claims appendedhereto, and by their equivalents.

Further, in describing representative embodiments of the presentinvention, the specification may have presented the method and/orprocess of the present invention as a particular sequence of steps.However, to the extent that the method or process does not rely on theparticular order of steps set forth herein, the method or process shouldnot be limited to the particular sequence of steps described. As one ofordinary skill in the art would appreciate, other sequences of steps maybe possible. Therefore, the particular order of the steps set forth inthe specification should not be construed as limitations on the claims.In addition, the claims directed to the method and/or process of thepresent invention should not be limited to the performance of theirsteps in the order written, and one skilled in the art can readilyappreciate that the sequences may be varied and still remain within thespirit and scope of the present invention.

1. An arrangement for compensation of a magnetic bias field in a storagelayer of at least one magnetoresistive memory cell provided in asemiconductor device, comprising: at least one compensation layer thatis provided with a magnetization compensates for the bias field in thestorage layer.
 2. The arrangement of claim 1, wherein the compensationlayer is situated within the semiconductor device.
 3. The arrangement ofclaim 1, wherein the compensation layer is situated outside thesemiconductor device.
 4. The arrangement of claim 2, wherein thecompensation layer is isolated from the memory cell by at least oneinsulation layer.
 5. The arrangement of claim 1, wherein the magneticfield generated by the compensation layer runs parallel to the storagelayer and generally extends over the cross-sectional area of thesemiconductor device.
 6. The arrangement of claim 1, wherein thecompensation layer is patterned for fine adjustment.
 7. A method forcompensation of a magnetic bias field in a storage layer of amagnetoresistive memory cell provided in a semiconductor device,comprising: applying a ferromagnetic compensation layer; measuring abias field in terms of magnitude and direction; and compensating thebias field by magnetization of the compensation layer.
 8. The method asin claim 7, wherein the measurement and compensation of the bias fieldare repeated at least once in order to preclude an erroneouscompensation due to a premagnetization of the compensation layer.
 9. Themethod of claim 7, wherein the compensation layer is applied within thesemiconductor device.
 10. The method of claim 7, wherein thecompensation layer is applied outside the semiconductor device.
 11. Themethod of claim 10, wherein the compensation layer is patterned.
 12. Amethod for compensation of a magnetic bias field in a storage layer of amagnetoresistive memory cell provided in a semiconductor device,comprising: measuring a bias field in terms of magnitude and direction,and compensating the bias field by application of a compensation layer,which has a magnetization that compensates for the bias field in thestorage layer.
 13. The method of claim 12, wherein measured values of ameasurement variable that characterizes the magnitude and direction ofthe magnetic bias field are determined by a measuring apparatus in atest mode of the semiconductor device and are transmitted to a testapparatus.
 14. The method of claim 13, wherein the measuring apparatuscontrols two mutually orthogonal measurement currents parallel to thestorage layer, which generate two magnetic measurement fields that areorthogonal to one another, and in that a magnetic-field-dependentcharacteristic variable of the memory cell is in each case determinedfor different pairs of values of the measurement fields by means of ameasuring device.
 15. The method of claim 12, wherein the measuringapparatus is provided at least partially within the semiconductordevice.
 16. The method of claim 12, wherein the compensation layer isapplied as a film with which the semiconductor device is inscribed.